A processor with separate decode and register fetch stages will probably have a ____________
A processor with separate decode and register fetch stages will probably have a ____________
If the program____________
If the program____________
In the following instruction set DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, all the instructions after the DADD use the result of the _____________
In the following instruction set DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, all the instructions after the DADD use the result of the _____________
Pipeline interlock introduces a stall or bubble, just as in the ___________
Pipeline interlock introduces a stall or bubble, just as in the ___________
For execution, branch instructions require 2 cycles, store instructions require 4 cycles, and all other instructions require _____________
For execution, branch instructions require 2 cycles, store instructions require 4 cycles, and all other instructions require _____________
If the buffer is a queue with multiple instructions, it stalls when the queue ______________
If the buffer is a queue with multiple instructions, it stalls when the queue ______________
The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is ____________
The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is ____________
The execution cycle with a branch, delay of one is_______________
The execution cycle with a branch, delay of one is_______________
The instruction in different stages of the pipeline do not interfere with one another, the separation is done by ______________
The instruction in different stages of the pipeline do not interfere with one another, the separation is done by ______________
Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is ______________
Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is ______________
The simplest scheme to handle branches is to _____________
The simplest scheme to handle branches is to _____________
The time required between moving an instruction one step down the pipeline is a________________
The time required between moving an instruction one step down the pipeline is a________________
MIPS pipeline with the appropriate registers, called pipeline registers or also known as ______________
MIPS pipeline with the appropriate registers, called pipeline registers or also known as ______________
If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a _____________
If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a _____________
Splitting the cache into separate instruction and data caches or by using a set of buffers, usually called ______________
Splitting the cache into separate instruction and data caches or by using a set of buffers, usually called ______________
If any instruction in A1, . . . , A4, D, M1, . . . , M7 has the same register destination as this instruction, then the possible solution is _____________
If any instruction in A1, . . . , A4, D, M1, . . . , M7 has the same register destination as this instruction, then the possible solution is _____________
Instruction used in sequences to implement a more complex instruction set, is called a ________________
Instruction used in sequences to implement a more complex instruction set, is called a ________________
A floating-point divider, a floating-point multiplier, and a floating-point adder, are the parts of a_____________
A floating-point divider, a floating-point multiplier, and a floating-point adder, are the parts of a_____________
The processor without the structural hazard is ______________
The processor without the structural hazard is ______________
If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to ______________
If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to ______________